View H5PS1G83EFR-E3L_6731323.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 this document is a general product descript ion and is subject to change without notic e. hynix semiconductor does not assume any responsibility for use of circuits descr ibed. no patent licenses are implied. rev. 1.1 / oct. 2010 1 h5ps1g83efr series 1gb ddr2 sdram h5ps1g83efr-xxc h5ps1g83efr-xxi h5ps1g83efr-xxl h5ps1g83efr-xxj h5ps1g83efr-g7x b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 2 release h5ps1g83efr series revision details rev. history draft date 1.0 released aug. 2009 1.1 idd specification update @1066 idd update oct. 2010 b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 3 release h5ps1g83efr series contents 1. description 1.1 device features and ordering information 1.1.1 key features 1.1.2 ordering information 1.1.3 operating frequency 1.2 pin configuration 1.3 pin description 2. maximum dc ratings 2.1 absolute maximum dc ratings 2.2 operating temperature condition 3. ac & dc oper ating conditions 3.1 dc operating conditions 3.1.1 recommended dc operating conditions(sstl_1.8) 3.1.2 odt dc electrical characteristics 3.2 dc & ac logic input levels 3.2.1 input dc logic level 3.2.2 input ac logic level 3.2.3 ac input test conditions 3.2.4 differential input ac logic level 3.2.5 differential ac output parameters 3.3 output buffer levels 3.3.1 output ac test conditions 3.3.2 output dc current drive 3.3.3 ocd default characteristics 3.4 idd specifications & measurement conditions 3.5 input/output capacitance 4 . ac timing specifications 5. package dimensions b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 4 release h5ps1g83efr series 1.1 device features & ordering information 1.1.1 key features ? vdd = 1.8 +/- 0.1v ? vddq = 1.8 +/- 0.1v ? all inputs and outputs are compatible with sstl_18 interface ?8 banks ? fully differential clock inputs (ck, /ck) operation ? double data rate interface ? source synchronous-data transaction alig ned to bidirectional data strobe (dqs, dqs ) ? differential data strobe (dqs, dqs ) ? data outputs on dqs, dqs edges when read (edged dq) ? data inputs on dqs centers when write (centered dq) ? on chip dll align dq, dqs and dqs transition with ck transition ? dm mask write data-in at the both risi ng and falling edges of the data strobe ? all addresses and control inputs except data, data strobes and da ta masks latched on the rising edges of the clock ? programmable cas latency 3, 4, 5 and 6 supported ? programmable additive latency 0, 1, 2, 3, 4 and 5 supported ? programmable burst length 4/8 with both nibble sequential and interleave mode ? internal eight bank operations with single pulsed ras ? auto refresh and self refresh supported ? tras lockout supported ? 8k refresh cycles /64ms ? jedec standard 60ball fbga(x8) ? full strength driver option controlled by emr ? on die termination supported ? off chip driver impedance adjustment supported ? self-refresh high temperature entry 1. description b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 5 release h5ps1g83efr series ordering information note: -xx* is the speed bin, refer to the operatin g frequency table for complete part number. -xxp and xxq are the low current bin, refer to the idd specification table. - hynix halogen-free products are compliant to rohs. hynix supports lead & halogen free parts for each speed grad e with same specification, except lead free materials. we'll add "r" character after "f" for lead & halogen free products operating frequency note: -g7 is a special speed product used in electronic engineering for high speed storage of the working data of a consumer digital electronic device. part no. / status configura - tion power consumption operation temp package h5ps1g83efr-xx*c 128mx8 normal consumption commercial 60 ball fbga h5ps1g83efr-xx*i normal consumption industrial h5ps1g83efr-xx*l low power consumption (idd6 only) commercial h5ps1g83efr-xx*j low power consumption (idd6 only) industrial grade tck(ns) cl trcd trp unit e3 5 3 3 3 clk c4 3.75 4 4 4 clk y5 3 5 5 5 clk s6 2.5 6 6 6 clk s5 2.5 5 5 5 clk g7 1.875 7 7 7 clk b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 6 release h5ps1g83efr series ? 1.2 pin configuration & address table 128mx8 ddr2 pin configuration (top view: see balls through package) row and column address table items 128mx8 # of bank 8 bank address ba0, ba1, ba2 auto precharge flag a10/ap row address a0 - a13 column address a0-a9 page size 1 kb vss dm/rdqs vddq dq3 vss we ba1 a1 a5 a9 nc nu/rdqs vssq dq1 vssq vref cke ba0 a10 a3 a7 a12 vdd dq6 vddq dq4 vddl ba2 vss vdd a b c d e f g h j k vssq dqs vddq dq2 vssdl ras cas a2 a6 a11 nc dqs vssq dq0 vssq ck ck cs a0 a4 a8 a13 vddq dq7 vddq dq5 vdd odt vdd vss l 3 2 1 78 9 b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 7 release h5ps1g83efr series 1.3 pin description pin type description ck, ck input clock : ck and ck are differential clock inputs. all address and control input signals are sampled on the crossing of the positive e dge of ck and negative edge of ck . output (read) data is refer- enced to the crossings of ck and ck (both directions of crossing). cke input clock enable : cke high activates, and cke low deactiva tes internal clock signals, and device input buffers and output drivers. taking cke low provides precharge power down and self refresh operation (all banks idle), or active po wer down (row active in any bank). cke is synchronous for power down entry and exit, an d for self refresh entry. cke is asynchro- nous for self refresh exit. after v ref has become stable during the power on and initialization sequence, it must be maintained for proper operat ion of the cke receiver. for proper self-refresh entry and exit, v ref must be maintained to this input. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck and cke are disabled during power down. input buffers, excluding cke are disabled during self refresh. cs input chip select : all commands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. odt input on die termination control : odt (registered high) enables on die termination resistance internal to the ddr2 sdram. when enabled, odt is only applied to dq, dqs, dqs , rdqs, rdqs , and dm signal for x4,x8 configurations. for x16 configuration odt is applied to each dq, udqs/udqs .ldqs/ldqs , udm and ldm signal. the odt pin will be ignored if the extended mode register(emr(1)) is programmed to disable odt. ras , cas , we input command inputs : ras , cas and we (along with cs ) define the command being entered. dm (ldm, udm) input input data mask : dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with th at input data during a write access. dm is sampled on both edges of dqs, although dm pins are input only, the dm loadin g matches the dq and dqs load- ing. for x8 device, the func tion of dm or rdqs/ rdqs is enabled by emr command to emr(1). ba0 - ba2 input bank address inputs : ba0 - ba2 define to which bank an active, read, write or precharge command is being applied (for 256mb and 512mb, ba2 is not applied). bank address also deter- mines if one of the mode register or extended mo de register is to be accessed during a mr or emr command cycle. a0 -amax input address inputs : provide the row address for active commands, and the column address and auto precharge bit for read/write commands to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by ba0-ba2. the address inpu ts also provide the op code during mrs or emrs commands. dq input/output data input / output : bi-directional data bus dqs, (dqs) (udqs),(udqs ) (ldqs),(ldqs ) (rdqs),(rdqs ) input/output data strobe : output with read data, input with write data. edge aligned with read data, cen- tered in write data. for the x16, ldqs correspo nd to the data on dq0~dq7; udqs corresponds to the data on dq8~dq15. for the x8, an rdqs option using dm pin can be enabled via the emr(1) to simplify read timing. the data strobe s dqs, ldqs, udqs, and rdqs may be used in single ended mode or paired with optional complementary signals dq s, ldqs,udqs and rdqs to provide differential pair signaling to the system during both reads and writes. an emr(1) con- trol bit enables or disables all complementary data strobe signals. in this data sheet, "differential dqs signals" refers to any of the following with a10 = 0 of emr(1) x4 dqs/dqs x8 dqs/dqs if emr(1)[a11] = 0 x8 dqs/dqs , rdqs/rdqs , if emr(1)[a11] = 1 x16 ldqs/ldqs and udqs/udqs "single-ended dqs signals" refers to an y of the following with a10 = 1 of emr(1) x4 dqs x8 dqs if emr(1)[a11] = 0 x8 dqs, rdqs, if emr(1)[a11] = 1 x16 ldqs and udqs b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 8 release h5ps1g83efr series -continued- pin type description nc no connect : no internal electrical connection is present. v ddq supply dq power supply : 1.8v +/- 0.1v vssq supply dq ground v ddl supply dll power supply : 1.8v +/- 0.1v v ssdl supply dll ground vdd supply power supply : 1.8v +/- 0.1v v ss supply ground v ref supply reference voltage . b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 9 release h5ps1g83efr series 2. maximum dc ratings 2.1 absolute maxi mum dc ratings note: 1. stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operat ion of the device at these or any other conditions above those indicated in the operational sectio ns of this specification is not implie d. exposure to absolute maximum rat- ing conditions for extended periods may affect reliability. 2. storage temperature is the case surface temperature on the center /top side of the dram. for the measurement conditions. please refer to jesd51-2 standard. 2.2 operating temperature condition note: ? 1. operating temperature is the case surface temperature on the center/top side of the dram. for the measure- ment conditions, please refer to jesd51-2 standard. 2. at 85~95 t oper , double refresh rate(trefi: 3.9us) is required, and to enter the self refresh mode at this tem- perature range it must be required an emrs command to change itself refresh rate. symbol parameter rating units notes vdd voltage on vdd pin relative to vss - 1.0 v ~ 2.3 v v 1 vddq voltage on vddq pin relative to vss - 0.5 v ~ 2.3 v v 1 vddl voltage on vddl pin relative to vss - 0.5 v ~ 2.3 v v 1 v in, v out voltage on any pin relative to vss - 0.5 v ~ 2.3 v v 1 t stg storage temperature -55 to +100 ? c 1, 2 i i input leakage current; any input 0v vin vdd; all other balls not under test = 0v) -2 ua ~ 2 ua ua i oz output leakage current; 0v vout vddq; dq and odt disabled -5 ua ~ 5 ua ua symbol parameter rating units notes t oper operating temperature commercial 0 to 95 ? c 1,2 industrial -40 to 95 b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 10 release h5ps1g83efr series 3. ac & dc operating conditions 3.1 dc operating conditions 3.1.1 recommended dc operating conditions (sstl_1.8) note: 1. min. typ. and max. values increase by 100mv for c3(ddr2-533 3-3-3) speed option. 2. vddq tracks with vdd,vddl tracks with vdd. ac parameters are measured with vdd,vddq and vdd. 3. the value of vref may be selected by the user to pr ovide optimum noise margin in the system. typically the value of vref is expected to be about 0.5 x vddq of the transmitting device and vref is expected to track varia- tions in vddq 4. peak to peak ac noise on vref may not exceed +/-2% vref (dc). 5. vtt of transmitting device must track vref of receiving device. 3.1.2 odt dc electrical characteristics ? note: 1. test condition for rtt measurements measurement definition for rtt(eff): apply v ih (ac) and v il (ac) to test pin separately, then measure current i(v ih (ac)) and i(v il (ac)) respectively. v ih (ac), v il (ac), and vddq values defined in sstl_18 measurement definition for vm: measurement volt age at test pin (mid point) with no load. symbol parameter rating units notes min. typ. max. vdd supply voltage 1.7 1.8 1.9 v 1 vddl supply voltage for dll 1.7 1.8 1.9 v 1,2 vddq supply voltage for output 1.7 1.8 1.9 v 1,2 vref input reference voltage 0.49*vddq 0.50*vddq 0.51*vddq mv 3,4 vtt termination voltage vref-0.04 vref vref+0.04 v 5 parameter/condition symbol min nom max units notes rtt effective impedance value for emr(a6,a2)=0,1; 75 ohm rtt1(eff) 60 75 90 ohm 1 rtt effective impedance value for emr(a6,a2)=1,0; 150 ohm rtt2(eff) 120 150 180 ohm 1 rtt effective impedance value for emr(a6,a2)=1,1; 50 ohm rtt3(eff) 40 50 60 ohm 1 deviation of vm with respect to vddq/2 delta vm -6 +6 % 1 rtt(eff) = v ih (ac) - v il (ac) i(v ih (ac)) - i(v il (ac)) delta vm =( 2 x vm vddq x 100% - 1) b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 11 release h5ps1g83efr series 3.2 dc & ac logic input levels 3.2.1 input dc logic level 3.2.2 input ac logic level 3.2.3 ac input test conditions note: 1. input waveform timing is referenced to the input signal crossing through the v ref level applied to the device ? under test. 2. the input signal minimum slew rate is to be maintained over the range from v ref to v ih(ac) min for rising ? edges and the range from v ref to v il(ac) max for falling edges as shown in the figure below. 3. ac timings are referenced with input waveforms switchin g from vil(ac) to vih(ac) on the positive transitions ? and vih(ac) to vil(ac) on the negative transitions. symbol parameter min. max. units notes v ih (dc) dc input logic high vref + 0.125 vddq + 0.3 v v il (dc) dc input logic low - 0.3 vref - 0.125 v symbol parameter ddr2 400,533 ddr2 667,800 units notes min. max. min. max. v ih (ac) ac input logic high vref + 0.250 vddq+vpeak v ref + 0.200 vddq+vpeak v v il (ac) ac input logic low vssq-vpeak vref - 0.250 vssq-vpeak vref - 0.200 v symbol parameter ddr2 1066 units notes min. max. v ih (ac) ac input logic high vref + 0.200 vddq+vpeak v v il (ac) ac input logic low vssq-vpeak vref - 0.200 v symbol condition value units notes v ref input reference voltage 0.5 * v ddq v1 v swing(max) input signal maximum peak to peak swing 1.0 v 1 slew input signal minimum slew rate 1.0 v/ns 2, 3 v ddq v ih(ac) min v ref v swing(max) delta tr delta tf v ih(dc) min v il(dc) max v il(ac) max v ss rising slew = delta tr v ih(ac) min - v ref v ref - v il(ac) max delta tf falling slew = b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 12 release h5ps1g83efr series 3.2.4 differential input ac logic level note: 1. vin(dc) specifies the allowable dc execution of each input of differential pair such as ck, ck , dqs, dqs , ldqs, ? ldqs , udqs and udqs . 2. vid(dc) specifies the input differential voltage |vtr -vcp | required for switching, where vtr is the true input (such as ck, dqs, ldqs or udqs) level and vcp is the complementary input (such as ck , dqs , ldqs or udqs ) level. ? the minimum value is equa l to vih(dc) - v il(dc). note: 1. vid(ac) specifies the input differential voltage |vtr -vcp | required for switching, where vtr is the true input sig- nal ? (such as ck, dqs, ldqs or udqs) and vcp is the complementary input signal (such as ck , dqs , ldqs or udqs ). the minimum value is equal to v ih(ac) - v il(ac). 2. the typical value of vix(ac) is expected to be about 0.5 * vddq of the transmitting device and vix(ac) is expected to track variations in vddq. vix(ac) indicates th e voltage at which differenti al input signals must cross. 3.2.5 differential ac output parameters note: 1. the typical value of vox(ac) is expected to be about 0.5 * v ddq of the transmitting device and vox(ac) is expected to track variations in vd dq. vox(ac) indicates the voltage at which differential output signals must cross. symbol parameter min. max. units notes v id (ac) ac differential input voltage 0.5 vddq + 0.6 v 1 v ix (ac) ac differential cross point voltage 0.5 * vddq - 0.175 0.5 * vddq + 0.175 v 2 symbol parameter min. max. units notes v ox (ac) ac differential cross point voltage 0.5 * vddq - 0.125 0.5 * vddq + 0.125 v 1 v ddq crossing point v ssq v tr v cp v id v ix or v ox < differential signal levels > b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 13 release h5ps1g83efr series 3.3 output buffer characteristics 3.3.1 output ac test conditions note: 1. the vddq of the device under test is referenced. 3.3.2 output dc current drive note: 1. v ddq = 1.7 v; v out = 1420 mv. (v out - v ddq )/i oh must be less than 21 ohm for values of v out between v ddq ? and v ddq - 280 mv. 2. v ddq = 1.7 v; v out = 280 mv. v out /i ol must be less than 21 ohm for values of v out between 0 v and 280 mv. 3. the dc value of v ref applied to the receiving device is set to v tt 4. the values of i oh(dc) and i ol(dc) are based on the conditions given in notes 1 and 2. they are used to test ? device drive current capability to ensure v ih min plus a noise margin and v il max minus a noise margin are ? delivered to an sstl_18 receiver. the actual current values are derived by shifting the desired driver operating ? point (see section 3.3) along a 21 oh m load line to define a convenient driver current for measurement. symbol parameter sstl_18 class ii units notes v otr output timing measurement reference level 0.5 * v ddq v1 symbol parameter sstl_18 units notes i oh(dc) output minimum source dc current - 13.4 ma 1, 3, 4 i ol(dc) output minimum sink dc current 13.4 ma 2, 3, 4 b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 14 release h5ps1g83efr series 3.3.3 ocd default characteristics note : 1. absolute specifications ( toper; vdd = +1.8v 0.1v, vddq = +1.8v 0.1v) 2. impedance measurement condition for output source dc current: vddq=1.7v; vout=1420mv; (vout- vddq)/ioh must be less than 23.4 ohms for values of vout between vddq and vddq-280mv. ? impedance measurement condition for output sink dc cu rrent: vddq = 1.7v; vout = 280mv; vout/iol must be ? less than 23.4 ohms for values of vout between 0v and 280mv. 3. mismatch is absolute value between pull-up and pull-d n, both are measured at same temperature and voltage. 4. slew rate measured from vil(ac) to vih(ac). 5. the absolute value of the slew rate as measured from dc to dc is equal to or greater than the slew rate as ? measured from ac to ac. this is guaranteed by design and characterization. 6. this represents the step size when the ocd is ne ar 18 ohms at nominal conditions across all process ? corners/variations and represents only the dram uncertaint y. a 0 ohm value(no calibration) can only be achieved if the ocd impedance is 18 ohms +/- 0.75 ohms under nominal conditions. ? ? output slew rate load: ? ? ? ? ? ? ? ? ? ? ? ? ? ? 7. dram output slew rate specification a pplies to 400, 533 and 667 mt/s speed bins. 8. timing skew due to dram output slew rate mis-match between dqs / dqs and associated dqs is included in tdqsq and tqhs specification. description parameter min nom max unit notes output impedance - - - ohms 1 output impedance step size for ocd calibration 0 1.5 ohms 6 pull-up and pull-down mismatch 0 4 ohms 1,2,3 output slew rate sout 1.5 - 5 v/ns 1,4,5,6,7,8 vtt 25 ohms output (vout) reference point b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 15 release h5ps1g83efr series idd specifications(max) - i note : product list symbol ddr2 400 ddr2 533 ddr2 667 ddr2 800 ddr2 1066 units x8 x8 x8 x8 x8 idd0 60 65 70 75 90 ma idd1 70 75 80 85 105 ma idd2p 10 10 10 10 10 ma idd2q 22 27 30 32 35 ma idd2n 30 35 40 45 50 ma idd3p f 25 25 25 25 25 ma s 12 12 12 12 12 ma idd3n 40 45 50 55 65 ma idd4w 100 120 145 170 220 ma idd4r 100 120 140 160 190 ma idd5 160 160 165 170 180 ma idd6 normal 10 10 10 10 10 ma low power 55555ma idd7 190 190 195 230 240 ma part no. configuration power consumption operation temp package h5ps1g83efr-xx*c 128mx8 normal consumption commercial 60 ball fbga h5ps1g83efr-xx*i normal consumption industrial h5ps1g83efr-xx*l low power consumption (idd6 only) commercial h5ps1g83efr-xx*j low power consumption (idd6 only) industrial 3.4 idd specifications & test conditions b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 16 release h5ps1g83efr series idd test conditions (idd values are for full operating range of voltage and temperature, notes 1-5) symbol conditions units idd0 operating one bank active-precharge current ; t ck = t ck(idd), t rc = t rc(idd), t ras = t ras min(idd); cke is high, cs is high between valid commands; address bus inputs are switch- ing;data bus inputs are switching ma idd1 operating one bank active-read-precharge current ; iout = 0ma;bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t rc = t rc (idd), t ras = t rasmin(idd), t rcd = t rcd(idd); cke is high, cs is high between valid commands; address bus in puts are switching; data pattern is same as idd4w ma idd2p precharge power-down current ; all banks idle; t ck = t ck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating ma idd2q precharge quiet standby current ;all banks idle; t ck = t ck(idd);cke is high, cs is high; other control and address bus inputs ar e stable; data bus inputs are floating ma idd2n precharge standby current ; all banks idle; t ck = t ck(idd); cke is high, cs is high; other control and address bus inputs are swit ching; data bus inputs are switching ma idd3p active power-down current ; all banks open; t ck = t ck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mr(12) = 0 ma slow pdn exit mr(12) = 1 ma idd3n active standby current ; all banks open; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching ma idd4w operating burst write current ; all banks open, continuous burst writes; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid commands; address bus inputs are sw itching; data bus inputs are switching ma idd4r operating burst read current ; all banks open, continuous burst reads, iout = 0ma; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs is high between valid commands; address bus inpu ts are switching; data pattern is same as idd4w ma idd5b burst refresh current ; t ck = t ck(idd); refresh command at every t rfc(idd) interval; cke is high, cs is high between valid commands; other co ntrol and address bus inputs are switch- ing; data bus inputs are switching ma idd6 self refresh current ; ck and ck at 0v; cke ? 0.2v; other control and address bus inputs are floating; data bus inputs are floating ma idd7 operating bank interleave read current ; all bank interleaving reads, iout = 0ma; bl = 4, cl = cl(idd), al = t rcd(idd)-1* t ck(idd); t ck = t ck(idd), t rc = t rc(idd), t rrd = t rrd(idd), t rcd = 1* t ck(idd); cke is high, cs is high between valid commands; address bus inputs are stable during deselects; data pattern is same as idd4r; - refer to the following page for detailed timing conditions ma b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 17 release h5ps1g83efr series note : 1. vddq = 1.8 +/- 0.1 v ; vdd = 1.8 +/- 0 .1 v ( exclusively vddq = 1.9 +/- 0.1 v ; vdd = 1.9 +/- 0 .1 v for c3 speed grade) 2. idd specifications are tested after the device is properly initialized 3. input slew rate is specified by ac parametric test condition 4. idd parameters are specified with odt disabled. 5. data bus consists of dq, dm, dqs, dqs , rdqs, rdqs , ldqs, ldqs , udqs, and udqs . idd values must be met with all combinations of emr bits 10 and 11. 6. for ddr2-667/800 testing, tck in the conditions should be interpreted as tck (avg). 7. definitions for idd ? low is defined as vin ? vilac (max) ? high is defined as vin ? vihac (min) ? stable is defined as inputs stable at a high or low level ? floating is defined as inputs at vref = vddq/2 ? switching is defined as: inputs changing between high and low every other clock cycle (once per two clocks) ? for address and control signals, and in puts changing between high and low every other data transfer (once per ? clock) for dq signals not including masks or strobes. ? b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 18 release h5ps1g83efr series idd testing parameters for purposes of idd testing, the following parameters are to be utilized . detailed idd7 the detailed timings are shown below for idd7. changes will be required if timi ng parameter changes are made to the specification. legend: a = active; ra = read with autoprecharge; d = deselect idd7: operating current: all bank interleave read operation all banks are being interleaved at minimum t rc(idd) without violating t rrd(idd) and tfaw (idd) using a burst length of 4. control and address bus inputs ar e stable during deselects. iout = 0ma timing patterns for 4 bank devices x4/ x8/ x16 -ddr2-400 4/4/4: a0 ra0 a1 ra1 a2 ra2 a3 ra3 d d d d d -ddr2-400 3/3/3: a0 ra0 a1 ra1 a2 ra2 a3 ra3 d d d d -ddr2-533 4/4/4: a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d d d d -ddr2-533 4/4/4: a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d d d d -ddr2-667 5/5/5: a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d -ddr2-667 4/4/4: a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d -ddr2-800 6/6/6: a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d d d d d -ddr2-800 5/5/5: a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d d d d -ddr2-800 4/4/4: a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d d d timing patterns for 8 bank devices x4/8 -ddr2-400 all bins: a0 ra0 a1 ra1 a2 ra2 a3 ra3 a4 ra4 a5 ra5 a6 ra6 a7 ra7 -ddr2-533 all bins: a0 ra0 a1 ra1 a2 ra2 a3 ra3 d d a4 ra4 a5 ra5 a6 ra6 a7 ra7 d d -ddr2-667 all bins: a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d a4 ra4 d a5 ra5 d a6 ra6 d a7 ra7 d d -ddr2-800 all bins: a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d d a4 ra4 d a5 ra5 d a6 ra6 d a7 ra7 d d d ddr2-800 ddr2- 667 ddr2- 533 ddr2- 400 parameter 5-5-5 6-6-6 5-5-5 4-4-4 3-3-3 units cl(idd) 5 6 5 4 3 tck t rcd(idd) 12.5 15 15 15 15 ns t rc(idd) 57.5 60 60 60 55 ns t rrd(idd)-x4/x8 7.5 7.5 7.5 7.5 7.5 ns t rrd(idd)-x16 10 10 10 10 10 ns t ck(idd) 2.5 2.5 3 3.75 5 ns t rasmin(idd) 45 45 45 45 40 ns t rasmax(idd) 70000 70000 70000 70000 70000 ns t rp(idd) 12.5 15 15 15 15 ns t rfc(idd)-256mb 75 75 75 75 75 ns t rfc(idd)-512mb 105 105 105 105 105 ns t rfc(idd)-1gb 127.5 127.5 127.5 127.5 127.5 ns t rfc(idd)-2gb 197.5 197.5 197.5 197.5 197.5 ns b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 19 release h5ps1g83efr series timing patterns for 8 bank devices x16 -ddr2-400 all bins: a0 ra0 a1 ra1 a2 ra2 a3 ra3 d d a4 ra4 a5 ra5 a6 ra6 a7 ra7 d d -ddr2-533 all bins: a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d d a4 ra4 d a5 d a6 ra6 d a7 ra7 d d d -ddr2-667 all bins: a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d a4 ra4 d d a5 ra5 d d a6 ra6 d d a7 ra7 d d d -ddr2-800 all bins: a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d a4 ra4 d d a5 ra5 d d a6 ra6 d d a7 ra7 d d d d 3.5. input/output capacitance parameter symbol ddr2 400 ddr2 533 ddr2 667 ddr2 800 units min max min max min max input capacitance, ck and ck cck 1.0 2.0 1.0 2.0 1.0 2.0 pf input capacitance delta, ck and ck cdck x 0.25 x 0.25 x 0.25 pf input capacitance, all other input-only pins ci 1.0 2.0 1.0 2.0 1.0 1.75 pf input capacitance delta, all other input-only pins cdi x 0.25 x 0.25 x 0.25 pf input/output capacitance, dq, dm, dqs, dqs cio 2.5 4.0 2.5 3.5 2.5 3.5 pf input/output capacitance delta, dq, dm, dqs, dqs cdio x 0.5 x 0.5 x 0.5 pf b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 20 release h5ps1g83efr series 4. electrical characteristics & ac timing specification (t oper ; v ddq = 1.8 +/- 0.1v; v dd = 1.8 +/- 0.1v) refresh parameters by device density note: 1: if refresh timing is violated, data corruption may occur and the data must be re-written with valid data before a valid read can be executed. 2. this is an optional fe ature. for detailed information, please refer to ?o perating temperature condition? in this data sheet. ddr2 sdram speed bins and trcd, trp and trc for corresponding bin note : 1. 8 bank device precharge all allowance: trp for a precharge all command for an 8 bank device will equal to trp+1*tck, where t rp are the values for a single bank precharge , which are shown in the table above. 2. refer to specific notes 32. 3. refer to specific notes 3. parameter symbol 256mb 512mb 1gb 2gb 4gb units notes refresh to active/refresh command time trfc 75 105 127.5 195 327.5 ns 1 average periodic refresh interval trefi 0 t case 85 7.8 7.8 7.8 7.8 7.8 us 1 85 t case 95 3.9 3.9 3.9 3.9 3.9 us 1,2 speed ddr2-800 ddr2-667 ddr2-533 ddr2-400 units notes parameter min min min min min min bin(cl-trcd-trp) 5-5-5 6-6-6 4-4-4 5-5-5 4-4-4 3-3-3 cas latency 5 6 4 5 4 3 tck trcd 12.5 15 12 15 15 15 ns 2 trp *1 12.5 15 12 15 15 15 ns 2 tras 45 45 45 45 45 40 ns 2,3 trc 57.5 60 57 60 60 55 ns 2 b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 21 release h5ps1g83efr series timing parameters by speed grade (ddr2-400 and ddr2-533) parameter symbol ddr2-400 ddr2-533 unit note min max min max dq output access time from ck/ck tac -600 +600 -500 +500 ps dqs output access time from ck/ck tdqsck -500 +500 -450 +450 ps ck high pulse width tch 0.45 0.55 0.45 0.55 tck ck low pulse width tcl 0.45 0.55 0.45 0.55 tck ck half period thp min(tcl, tch) - min(tcl, tch) - ps 11,12 clock cycle time, cl=x tck 5000 8000 3750 8000 ps 15 dq and dm input setup time(differential strobe) tds(base) 150 - 100 - ps 6,7,8,20 ,28 dq and dm input hold time(differential strobe) tdh(base) 275 - 225 - ps 6,7,8,21 ,28 dq and dm input setup time(single ended strobe) tds(base) 25 --25 - ps 6,7,8,25 dq and dm input hold time(single ended strobe) tdh(base) 25 --25 - ps 6,7,8,26 control & address input pulse width for each input tipw 0.6 - 0.6 - tck dq and dm input pulse width for each input tdipw 0.35 - 0.35 - tck data-out high-impedance time from ck/ck thz - tac max - tac max ps 18 dqs low-impedance time from ck/ck tlz (dqs) tac min tac max tac min tac max ps 18 dq low-impedance time from ck/ck tlz (dq) 2*tac min tac max 2*tac min tac max ps 18 dqs-dq skew for dqs and associated dq signals tdqsq - 350 - 300 ps 13 dq hold skew factor tqhs - 450 - 400 ps 12 dq/dqs output hold time from dqs tqh thp - tqhs - thp - tqhs - ps write command to first dqs latching transition tdqss wl - 0.25 wl + 0.25 wl - 0.25 wl + 0.25 tck dqs input high pulse width tdqsh 0.35 - 0.35 - tck dqs input low pulse width tdqsl 0.35 - 0.35 - tck dqs falling edge to ck setup time tdss 0.2 - 0.2 - tck dqs falling edge hold time from ck tdsh 0.2 - 0.2 - tck mode register set command cycle time tmrd 2 - 2 - tck write preamble twpre 0.35 - 0.35 - tck write postamble twpst 0.4 0.6 0.4 0.6 tck 10 address and control input setup time tis 350 - 250 - ps 5,7,9,23 address and control input hold time tih 475 - 375 - ps 5,7,9,23 read preamble trpre 0.9 1.1 0.9 1.1 tck 19 read postamble trpst 0.4 0.6 0.4 0.6 tck 19 active to active command period for 1kb page size products (x4, x8) trrd 7.5 -7.5 - ns 4 active to active command period for 2kb page size products (x16) trrd 10 -10 - ns 4 b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 22 release h5ps1g83efr series parameter symbol ddr2-400 ddr2-533 units notes min max min max four active window for 1kb page size products tfaw 37.5 - 37.5 - ns four active window for 2kb page size products tfaw 50 -50 - ns cas to cas command delay tccd 2 2 tck write recovery time twr 15 - 15 - ns auto precharge write recovery + precharge time tdal wr+trp* - wr+trp* - tck 14 internal write to read command delay twtr 10 -7.5 - ns 24 internal read to precharge command delay trtp 7.5 7.5 ns 3 exit self refresh to a non-read command txsnr trfc + 10 trfc + 10 ns exit self refresh to a read command txsrd 200 - 200 - tck exit precharge power down to any non- read command txp 2 - 2 - tck exit active power down to read command txard 2 2 tck 1 exit active power down to read command (slow exit, lower power) txards 6 - al 6 - al tck 1, 2 cke minimum pulse width (high and low pulse width) tcke 3 3 tck 27 odt turn-on delay taond 2 2 2 2 tck 16 odt turn-on taon tac(min) tac(max) +1 tac(min) tac(max) +1 ns 16 odt turn-on(power-down mode) taonpd tac(min)+ 2 2tck+tac (max) +1 tac(min)+ 2 2tck+ta c(max)+1 ns odt turn-off delay taofd 2.5 2.5 2.5 2.5 tck 17,44 odt turn-off taof tac(min) tac(max) + 0.6 tac(min) tac(max) + 0.6 ns 17,44 odt turn-off (power-down mode) taofpd tac(min)+ 2 2.5tck+ta c(max)+1 tac(min)+ 2 2.5tck+t ac(max) +1 ns odt to power down entry latency tanpd 3 3 tck odt power down exit latency taxpd 8 8 tck ocd drive mode output delay toit 0 12 0 12 ns minimum time clocks remains on after cke asynchronously drops low tdelay tis+tck+ti h tis+tck+ti h ns 15 -continued- b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 23 release h5ps1g83efr series (ddr2-667 and ddr2-800) parameter symbol ddr2-667 ddr2-800 unit note min max min max dq output access time from ck/ck tac -450 +450 -400 +400 ps 40 dqs output access time from ck/ck tdqsck -400 +400 -350 +350 ps 40 ck high pulse width tch(avg) 0.48 0.52 0.48 0.52 tck(avg) 35,36 ck low pulse width tcl(avg) 0.48 0.52 0.48 0.52 tck(avg) 35,36 ck half period thp min(tcl(abs), tch(abs)) - min(tcl(abs), tch(abs)) - ps 37 clock cycle time, cl=x tck(avg) 3000 8000 2500 8000 ps 35,36 dq and dm input setup time tds(base) 100 - 50 - ps 6,7,8,20,28,31 dq and dm input hold time tdh(base) 175 - 125 - ps 6,7,8,21,28,31 control & address input pulse width for each input tipw 0.6 - 0.6 - tck(avg) dq and dm input pulse width for each input tdipw 0.35 - 0.35 - tck(avg) data-out high-impedance time from ck/ck thz - tac max - tac max ps 18,40 dqs low-impedance time from ck/ck tlz(dqs) tac min tac max tac min tac max ps 18,40 dq low-impedance time from ck/ck tlz(dq) 2*tac min tac max 2*tac min tac max ps 18,40 dqs-dq skew for dqs and associated dq signals tdqsq - 240 -200 ps 13 dq hold skew factor tqhs - 340 -300 ps 38 dq/dqs output hold time from dqs tqh thp - tqhs - thp - tqhs - ps 39 first dqs latching transition to associated clock edge tdqss - 0.25 + 0.25 - 0.25 + 0.25 tck(avg) 30 dqs input high pulse width tdqsh 0.35 - 0.35 - tck(avg) dqs input low pulse width tdqsl 0.35 - 0.35 - tck(avg) dqs falling edge to ck setup time tdss 0.2 - 0.2 - tck(avg) 30 dqs falling edge hold time from ck tdsh 0.2 - 0.2 - tck(avg) 30 mode register set command cycle time tmrd 2 - 2 - tck(avg) write preamble twpre 0.35 - 0.35 - tck(avg) write postamble twpst 0.4 0.6 0.4 0.6 tck(avg) 10 address and control input setup time tis(base) 200 -175 - ps 5,7,9,22,29 address and control input hold time tih(base) 275 -250 - ps 5,7,9,23,29 read preamble trpre 0.9 1.1 0.9 1.1 tck(avg) 19,41 read postamble trpst 0.4 0.6 0.4 0.6 tck(avg) 19,42 activate to precharge command tras 45 70000 45 70000 ns 3 active to active command period for 1kb page size products (x4, x8) trrd 7.5 -7.5 - ns 4,32 active to active command period for 2kb page size products (x16) trrd 10 -10 - ns 4,32 four active window for 1kb page size products tfaw 37.5 - 35 - ns 32 four active window for 2kb page size products tfaw 50 - 45 - ns 32 cas to cas command delay tccd 2 2 nck write recovery time twr 15 - 15 - ns 32 auto precharge write recovery + precharge time tdal wr+tnrp - wr+tnrp - nck 33 b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 24 release h5ps1g83efr series -continued- parameter symbol ddr2-667 ddr2-800 unit notes min max min max internal write to read command delay twtr 7.5 -7.5 - ns 24,32 internal read to precharge command delay trtp 7.5 7.5 ns 3,32 exit self refresh to a non-read command txsnr trfc + 10 trfc + 10 ns 32 exit self refresh to a read command txsrd 200 - 200 - nck exit precharge power down to any non-read command txp 2 - 2 - nck exit active power down to read command txard 2 2 nck 1 exit active power down to read command (slow exit, lower power) txards 7 - al 8 - al nck 1, 2 cke minimum pulse width (high and low pulse width) tcke 3 3 nck 27 odt turn-on delay taond 2 2 2 2 nck 16 odt turn-on taon tac(min) tac(max) +0.7 tac(min) tac(max) +0.7 ns 6,16,40 odt turn-on(power-down mode) taonpd tac(min)+2 2tck(avg)+ tac(max)+1 tac(min) +2 2tck(avg)+ tac(max)+1 ns odt turn-off delay taofd 2.5 2.5 2.5 2.5 nck 17,45 odt turn-off taof tac(min) tac(max)+ 0.6 tac(min) tac(max) +0.6 ns 17,43,4 5 odt turn-off (power-down mode) taofpd tac(min) +2 2.5tck(avg)+ tac(max)+1 tac(min) +2 2.5tck(avg)+ tac(max)+1 ns odt to power down entry latency tanpd 3 3 nck odt power down exit latency taxpd 8 8 nck ocd drive mode output delay toit 0 12 0 12 ns 32 minimum time clocks remains on after cke asynchronously drops low tdelay tis + tck (avg) + tih tis + tck (avg) + tih ns 15 b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 25 release h5ps1g83efr series general notes, which may ap ply for all ac parameters 1. ddr2 sdram ac timing reference load the following figure represents the timing referenc e load used in defining the relevant timing parameters of the part. it is not intended to be either a precis e representation of the typical system environment nor a depiction of the actual load presented by a production tester. system designers will use ibis or other simula- tion tools to correlate the timing reference load to a sy stem environment. manufacturers will correlate to their production test conditions (generally a coaxial tran smission line terminated at the tester electronics). ? the output timing reference voltage level for single ende d signals is the crosspoint with vtt. the output tim- ing reference voltage level for differential signals is the crosspoint of the true (e.g. dqs) and the complement (e.g. dqs ) signal. 2. slew rate measurement levels a. output slew rate for falling and rising e dges is measured between vtt - 250 mv and vtt + 250 mv for single ended signals. for differential signals (e.g. dqs - dqs ) output slew rate is measured between dqs - dqs = -500 mv and dqs - dqs = +500mv. output slew rate is guaranteed by design, but is not necessarily tested on each device. b. input slew rate for single ended signals is me asured from dc-level to ac-level: from vref - 125 mv to vref + 250 mv for rising edges and from vref + 125 mv and vref - 250 mv for falling edges. for differential signals (e.g. ck - ck ) slew rate for rising edges is measured from ck - ck = -250 mv to ck - ck = +500 mv (+250mv to -500 mv for falling edges). c. vid is the magnitude of the difference between the input voltage on ck and the input voltage on ck , or between dqs and dqs for differential strobe. 3. ddr2 sdram output slew rate test load output slew rate is characterize d under the test conditions as shown below. ? vddq dut dq dqs dqs rdqs rdqs output v tt = v ddq /2 25 ? timing reference point ac timing reference load vddq dut dq dqs, dqs rdqs, rdqs output v tt = v ddq /2 25 ? test point slew rate test load b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 26 release h5ps1g83efr series 4. differential data strobe ddr2 sdram pin timings are specified for either single ended mode or differential mode depending on the setting of the emr ?enable dqs? mode bit; timing adva ntages of differential mode are realized in system design. the method by which the ddr2 sdram pin timi ngs are measured is mode dependent. in single ended mode, timing relationships are measured relative to the rising or falling edges of dqs crossing at vref. in differential mode, these timing relationships are me asured relative to the crosspoint of dqs and its com - plement, dqs . this distinction in timing methods is guarante ed by design and characterization. note that when differential data strobe mode is disa bled via the emr, the complementary pin, dqs , must be tied exter - nally to vss through a 20 ? to 10 k ? resistor to insure proper operation. 5. ac timings are for linear signal transitions. see system derating for other signal transitions. 6. all voltages referenced to vss. 7. these parameters guarantee device behavior, but th ey are not necessarily tested on each device. they may be guaranteed by device design or tester correlation. 8. tests for ac timing, idd, and electrical (ac and dc) characteristics, may be conducted at nominal refer - ence/supply voltage levels, but the related specificatio ns and device operation are guaranteed for the full voltage range specified. t ds t ds t dh t wpre t wpst t dqsh t dqsl dqs dqs d dmin dqs/ dq dm t dh figure -- data input (write) timing dmin dmin dmin d d d dqs v ih (ac) v il (ac) v ih (ac) v il (ac) v ih (dc) v il (dc) v ih (dc) v il (dc) t ch t cl ck ck ck/ck dqs/dqs dq dqs dqs t rpst q t rpre t dqsqmax t qh t qh t dqsqmax figure -- data output (read) timing q q q b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 27 release h5ps1g83efr series specific notes for de dicated ac parameters 1. user can choose which active power down exit timi ng to use via mrs(bit 12). txard is expected to be used for fast active power down exit timing. txards is expected to be us ed for slow active power down exit timing where a lower power value is defined by each vendor data sheet. 2. al = additive latency 3. this is a minimum requirement. minimum read to pr echarge timing is al + bl/2 providing the trtp and tras(min) have been satisfied. 4. a minimum of two clocks (2 * tck or 2 * nck) is required irrespective of operating frequency 5. timings are specified with command/address input slew rate of 1.0 v/ns. see system derating for other slew rate values. 6. timings are guaranteed with dqs, dm, and dqs?s(dq s/rdqs in singled ended mo de) input slew rate of 1.0 v/ns. see system derating for other slew rate values. 7. timings are specified with ck/ ck differential slew rate of 2.0 v/ns. timings are guaranteed for dqs signals with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1v/ns in single ended mode. see system derating for other slew rate values. 8. tds and tdh derating td s tds tdh tds tdh td s tdh td s tdh td s td h tds td h tds td h tds tdh tds tdh 2.0 100 45 100 45 100 45 - - - - - - - - - - - - 1.56721672167217933 - - - - - - - - - - 1.000000012122424-------- 0.9 - - -5 -14 -5 -14 7 -2 19 10 31 22 - - - - - - 0.8 - - - - -13 -31 -1 -19 11 -7 23 5 35 17 - - - - 0.7 - - - - - --10-422-3014-1826-638 6 - - 0.6- -- -- ----10-592-4714-3526-2338-11 0.5- -- -- --- ---24-89-12-770-6512-53 0.4 - - - - - - - - - - - - -52 -140 -40 -128 -28 -116 1.8 v/ns 0.8 v/ns dq slew rate v/ns dqs, dqs differential slew rate tds, tdh derating values for ddr2-667, ddr2-800(all units in 'ps', note 1 applies to entire table) 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 4.0 v/ns 3.0 v/ns 2.0 v/ns b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 28 release h5ps1g83efr series 1) for all input signals the total tds(setup time) and tdh(hold ti me) required is calculated by adding the datasheet value to t he derating value listed in table x. setup(tds) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vref(dc) and the firs t crossing of vih(ac)min. setup(tds) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vref( dc) and the first crossing of vil(ac)max. if the actual signal is al ways earlier than the nominal slew rate line between shaded ? vref(dc) to ac region?, use nominal slew rate for derating value(see fig a.) if the actual signal is later than the nominal slew rate line anywhere bet ween shaded ?vref(dc) to ac region?, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for deratin g value(see fig b.) hold(tdh) nominal slew rate for a risi ng signal is defined as the slew rate between the last crossing of vil(dc) max and the first crossing of vref(dc). hold (tdh) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vih(dc) min and the first crossing of vref(dc). if the actual si gnal is always later than the nominal slew rate line anywhere between shaded ?dc to vref(dc) region?, the slew rate of a tangent line to the actual signal from the dc level to vref(dc) level is used for derating value(se e fig c.) if the actual signal is earlier than the nominal slew rate line anywhere between shaded ?dc to vref(dc) region?, the slew rate of a ta ngent line to the actual signal from the dc level to vref(dc) level is used for derating value(see fig d.) although for slow slew rates the total setup time might be nega tive(i.e. a valid input signal wi ll not have reached vih/il(ac) at the time of the rising clock transition) a valid input signal is stil l required to complete the transition and reach vih/il(ac). for slew rate in between the values li sted in table x, the derating valued may obtained by linear interpolation. these values are typically not subject to production test. they are verified by design and characterization. tds tdh tds tdh td s tdh td s tdh td s td h tds td h tds td h tds tdh tds tdh 2.018818816714612563-- -- -- -- -- -- 1.5 146 167 125 125 83 42 81 43 - - - - - - - - - - 1.063125428300-21-7-13-- -- -- -- 0 .9 - - 3 1 69 - 11 -1 4 - 13 -1 3 - 18 -2 7 - 29 -4 5 - - - - - - 0 .8 - - - - - 25 -3 1 - 27 -3 0 - 32 -4 4 - 43 -6 2 -6 0 -8 6 - - - - 0 .7 - - - - - - - 45 -5 3 - 50 -6 7 - 61 -8 5 -7 8 -1 09 - 10 8 -1 52 - - 0.6 - - - - - - - - -74 -96 -85 -114 -102 -138 -132 -181 -183 -248 0.5- -- -- --- ---128-156-145-180-175-223-226-288 0.4- -- -- --- -- ---210-243-240-286-291-351 td s, tdh derating values fo r d dr2-400, ddr2-533(all un its in 'ps', note 1 applies to entire table) 0.8 v/ns 0.7 v/ns 0.6 v/ns 0.5 v/ns 2.0 v/ns 1.5 v/ns 1.0 v/ns 0.9 v/ns 0.4 v/ns dq slew rate v/ns dqs, sin gle-ended slew r ate b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 29 release h5ps1g83efr series if the actual signal is earlier than the nominal slew rate line anywhere between shaded ?dc to v ref (dc) region?, the slew rate of a tangent line to the actual signal from the dc level to v ref (dc) level is used for derating value(see fig d.) ? ? although for slow rates the total setup time might be negative(i.e. a valid input signal will not have reached v ih/il (ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach v ih/il (ac). for slew rates in between the values listed in table, the derating values may obtained by linear interpola- tion. these values are typically not subject to production te st. they are verified by design and characterization. b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 30 release h5ps1g83efr series fig. a. illustration of no minal slew rate for tis,tds ck,dqs v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max vss delta tf delta tr v ref to ac region nominal slew rate nominal slew rate t is , t ds v ref (dc)-v il (ac)max setup slew rate falling signal = delta tf v ih (ac)min-v ref (dc) setup slew rate rising signal = delta tr t ih , t dh t is , t ds t ih , t dh ck, dqs b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 31 release h5ps1g83efr series fig. b. illustration of tangent line for tis,tds ck, dqs v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max vss delta tf delta tr v ref to ac region tangent line tangent line t is , t ds ck, dqs nomial line nominal line delta tr tangent line[v ih (ac)min-v ref (dc)] setup slew rate rising signal = tangent line[v ref (dc)-v il (ac)max] setup slew rate falling signal = delta tf t ih , t dh t is , t ds t ih , t dh b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 32 release h5ps1g83efr series fig. c. illustration of nominal line for tih, tdh ck, dqs v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max vss delta tr nominal slew rate nominal slew rate t is , t ds v ref (dc)-v il (dc)max hold slew rate rising signal = delta tr v ih (dc)min - v ref (dc) hold slew rate falling signal = delta tf dc to v ref region delta tf ck, dqs t ih , t dh t is , t ds t ih , t dh b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 33 release h5ps1g83efr series fig. d. illustration of ta ngent line for tih, tdh ck, dqs v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max vss delta tf tangent line tangent line t is , t ds ck, dqs nominal line dc to v ref region nominal line delta tr tangent line[v ih (ac)min-v ref (dc)] hold slew rate falling signal = delta tf tangent line[v ref (dc)-v il (ac)max] hold slew rate rising signal = delta tr t ih , t dh t is , t ds t ih , t dh b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 34 release h5ps1g83efr series 9. tis and tih (input setup and hold) derating ? tis tih tis tih tis tih units notes 4.0 +187 +94 +217 +124 +247 +154 ps 1 3.5 +179 +89 +209 +119 +239 +149 ps 1 3.0 +167 +83 +197 +113 +227 +143 ps 1 2.5 +150 +75 +180 +105 +210 +135 ps 1 2.0 +125 +45 +155 +75 +185 +105 ps 1 1.5 +83 +21 +113 +51 +143 +81 ps 1 1.0 +0 0 +30 +30 +60 +60 ps 1 0.9 -11 -14 +19 +16 +49 +46 ps 1 0.8 -25 -31 +5 -1 +35 +29 ps 1 0.7 -43 -54 -13 -24 +17 +6 ps 1 0.6 -67 -83 -37 -53 -7 -23 ps 1 0.5 -110 -125 -80 -95 -80 -65 ps 1 0.4 -175 -188 -145 -158 -115 -128 ps 1 0.3 -285 -292 -255 -262 -225 -232 ps 1 0.25 -350 -375 -320 -345 -290 -315 ps 1 0.2 -525 -500 -495 -470 -465 -440 ps 1 0.15 -800 -708 -770 -678 -740 -648 ps 1 0.1 -1450 -1125 -1420 -1095 -1390 -1065 ps 1 tis, tih derating values for ddr2-400, ddr2-533 command / address slew rate(v/ns) 2.0 v/ns ck, ck differential slew rate 1.5 v/ns 1.0 v/ns b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 35 release h5ps1g83efr series 1) for all input signals the total tis(setup time) and ti h(hold) time) required is calculated by adding the datasheet value to the derating value listed in above table. ? ? setup(tis) nominal slew rate for a ri sing signal is defined as the slew rate between the last crossing of v ref (dc) and the first crossing of v ih (ac)min. setup(tis) nomina l slew rate for a falling signal is defined as the slew rate between the last crossing of v ref (dc) and the first crossing of v il (ac)max. if the actual signal is always earlier than the nominal slew rate for line between shaded ?v ref (dc) to ac region?, use nominal slew rate for derating value(see fig a.) if the actual sign al is later than the nominal slew rate line anywhere between shaded ?v ref (dc) to ac region?, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value(see fig b.) hold(tih) nominal slew rate for a risi ng signal is defined as the slew rate between the last crossing of vil(dc)max and the first crossing of v ref (dc). hold(tih) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref (dc). if the actual signal is always later than the nominal slew rate line between shaded ?dc to v ref (dc) region?, use nominal slew rate for derating value(see fig.c) if the actual signal is earlier than the nominal slew ra te line anywhere between shaded ?dc to v ref (dc) region?, the slew rate of a tangent line to the actu al signal from the dc level to v ref (dc) level is used for derating value(see fig d.) ? ? although for slow rates the total setup time might be negative(i.e. a valid input si gnal will not have reached v ih/il (ac) at the time of the rising clock transition) a valid input signal is still requ ired to complete the transi - tion and reach v ih/il (ac). for slew rates in between the values listed in table, th e derating values may obtained by linear interpolation. these values are typically not subject to production te st. they are verified by de sign and characterization. tis tih tis tih tis tih units notes 4.0 +15 +94 +180 +124 +210 +154 ps 1 3.5 +143 +89 +173 +119 +203 +149 ps 1 3.0 +133 +83 +163 +113 +193 +143 ps 1 2.5 +120 +75 +150 +105 +180 +135 ps 1 2.0 +100 +45 +130 +75 +150 +105 ps 1 1.5 +67 +21 +97 +51 +127 +81 ps 1 1.0 0 0 +30 +30 +60 +60 ps 1 0.9 -5 -14 +25 +16 +55 +46 ps 1 0.8 -13 -31 +17 -1 +47 +29 ps 1 0.7-22-54+8-24+38+6ps 1 0.6 -34 -83 -4 -53 +26 -23 ps 1 0.5 -60 -125 -30 -95 0 -65 ps 1 0.4 -100 -188 -70 -158 -40 -128 ps 1 0.3 -168 -292 -138 -262 -108 -232 ps 1 0.25 -200 -375 -170 -345 -140 -315 ps 1 0.2 -325 -500 -395 -470 -265 -440 ps 1 0.15 -517 -708 -487 -678 -457 -648 ps 1 0.1 -1000 -1125 -970 -1095 -940 -1065 ps 1 tis, tih derating values for ddr2-667, ddr2-800 command / address slew rate(v/ns) 2.0 v/ns ck, ck differential slew rate 1.5 v/ns 1.0 v/ns b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 36 release h5ps1g83efr series 10. the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter, but system performance (b us turnaround) will degrade accordingly. 11. min (t cl, t ch) refers to the smaller of the actu al clock low time and the actual clock high time as provided to the device (i.e. this valu e can be greater than the minimum spec ification limits for t cl and t ch). for example, t cl and t ch are = 50% of the period, less the half period jitter (t jit(hp)) of the clock source, and less the half period jitter due to crosstalk (t jit(crosstalk)) into the clock traces. 12. t qh = t hp ? t qhs, where: thp = minimum half clock period for any given cycle an d is defined by clock high or clock low (tch, tcl). tqhs accounts for: 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of dqs on one transition followed by the worst case pull-in of dq on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variat ion of the output drivers. 13. tdqsq: consists of data pin skew and output pattern effects, and p-ch annel to n-channel variation of the output drivers as well as output slew rate mismatch between dqs/ dqs and associated dq in any given cycle. 14. t dal = (nwr) + (trp/tck): for each of the terms above, if not already an integer, ro und to the next highest integer. tck refers to the appli - cation clock period. nwr refers to th e t wr parameter stored in the mr. example: for ddr533 at t ck = 3.75 ns with t wr pr ogrammed to 4 clocks. tdal = 4 + (15 ns / 3.75 ns) clocks =4 +(4)clocks=8clocks. 15. the clock frequency is allowed to change during self?refresh mode or precharge power-down mode. in case of clock frequency change during precharge powe r-down, a specific procedure is required as described in section 2.9. 16. odt turn on time min is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max is when the odt resistan ce is fully on. both are measured from taond. 17. odt turn off time min is when the device starts to turn off odt resistance. odt turn off time max is when the bus is in high impedance. both are measured from taofd. ? 18. thz and tlz transitions occur in the same access time as valid data transitions. these parameters are referenced to a specific voltage level which specifies wh en the device output is no longer driving (thz), or begins driving (tlz). below figure shows a method to calculate the point when devi ce is no longer driving (thz), or begins driving (tlz) by measuring the signal at two different voltages. the actual voltage measure - ment points are not critical as long as the calculation is consistent. ? ? b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 37 release h5ps1g83efr series 19. trpst end point and trpre begin po int are not referenced to a specific voltage level but specify when the device output is no longer driving (trpst), or be gins driving (trpre). below figure shows a method to calculate these points when the device is no longer driving (trpst), or begins driving (trpre). below fig - ure shows a method to calculate these points when the device is no longer driving (trpst), or begins driv - ing (trpre) by measuring the signal at two different voltages. the actual voltage measurement points are not critical as long as the calculation is consistent. 20. input waveform timing with differential data stro be enabled mr[bit10] =0, is referenced from the input signal crossing at the v ih (ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the v il (ac) level to the differential data st robe crosspoint for a falling signal applied to the device under test. 21. input waveform timing with differential data stro be enabled mr[bit10]=0, is referenced from the input signal crossing at the v ih (dc) level to the differential data stro be crosspoint for a rising signal and v il (dc) to the differential data strobe crosspoint for a falling signal applied to the device under test. thz , trpst end point = 2*t1-t2 tlz , trpre begin point = 2*t1-t2 voh + xmv voh + 2xmv vol + 1xmv vol + 2xmv thz trpst end point vtt + 2xmv vtt + xmv vtt -xmv vtt - 2xmv tlz trpre begin point t1 t1 t2 t2 dqs v ddq v ih(ac) min v ih(dc) min tdh tds dqs v ref (dc) v ss v il(dc) max v il(ac) max tdh tds differential input waveform timing b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 38 release h5ps1g83efr series 22. input waveform timing is referenced from the input signal crossing at the v ih (ac) level for a rising sig - nal and v il (ac) for a falling signal appl ied to the device under test. 23. input waveform timing is referenced from the input signal crossing at the v il (dc) level for a rising sig - nal and v ih (dc) for a falling signal appl ied to the device under test. 24. twtr is at least two clocks (2 x tck or 2 x nck) independent of operation frequency. 25. input waveform timing with single-ended data st robe enabled mr[bit10] = 1, is referenced from the input signal crossing at the vih (ac) level to the sing le-ended data strobe crossing vih/l (dc) at the start of its transition for a rising signal, and from the input signal crossing at the vil (ac) level to the single- ended data strobe crossing vih/l (dc) at the start of its transition for a falling signal applied to the device under test. the dqs signal must be monoto nic between vil(dc)max and vih (dc) min. 26. input waveform timing with single-ended data st robe enabled mr[bit10] = 1, is referenced from the input signal crossing at the vih(dc) level to the single -ended data strobe crossing vih/l(ac) at the end of its transition for a rising signal, and from the input si gnal crossing at the vil(dc ) level to the single-ended data strobe crossing vih/l(ac) at the end of its transi tion for a falling signal a pplied to the device under test. the dqs signal must be monotoni c between vil(dc)max and vih (dc) min. 27. tckemin of 3 clocks means cke must be register ed on three consecutive positive clock edges. cke must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. thus, after any cke transition, cke may not transition from its valid level during the time period of tis + 2 x tck + tih. 28. if tds or tdh is violated, data corruption may occu r and the data must be re -written with valid data before a valid read can be executed. 29. these parameters are measured from a command/a ddress signal (cke, cs, ras, cas, we, odt, ba0, a0, a1, etc.) transition edge to its respective cloc k signal (ck/ck) crossing. the spec values are not affected by the amount of clock jitte r applied (i.e. tjit (per), tjit (cc), et c.), as the setup and hold are rel - ative to the clock signal crossing that latches the command/address. that is, th ese parameters should be met whether clock jitter is present or not. 30. these parameters are measured from a data strobe signal ((l/u/r)dqs/dqs) cr ossing to its respective clock signal (ck/ck) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. tjit (per), tjit (cc), etc.), as these are relative to the clock signal crossing. that is, these parameters should be met whether clock jitter is present or not. 31. these parameters are measured from a data signal ((l/u) dm, (l/u) dq0, (l/u) dq1, etc.) transition edge to its respective data strobe signal ((l/u/r)dqs/dqs) crossing. 32. for these parameters, the ddr2 sdram device is characterized and verified to support tnparam = ru {tparam / tck (avg)}, which is in clock cy cles, assuming all input clock jitter specifications b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 39 release h5ps1g83efr series are satisfied. for example, the device will support tnrp = ru {trp / tck (avg)}, which is in clock cycles, if all input clock jitter specifications are met. this means: for ddr2-667 5-5-5, of which trp = 15ns, the device will support tnrp =ru {trp / tck (avg)} = 5, i.e. as long as th e input clock jitter specifications are met, precharge command at tm and active command at tm+5 is valid even if (tm+5 - tm) is less than 15ns due to input clock jitter. 33. tdal [nck] = wr [nck] + tnrp [nck] = wr + ru {trp [ps] / tck (avg) [ps]}, where wr is the value programmed in the mode register set. 34. new units, ?tck (avg)? and ?nck?, are introduced in ddr2-667 and ddr2-800. unit ?tck (avg)? represents the actual tc k (avg) of the input clock under operation. unit ?nck?, represents one clock cycle of the input clock, counting the actual clock edges. note that in ddr2-400 and ddr2-533, ?t ck?, is used for both concepts. ex) txp = 2 [nck] means; if power down exit is regi stered at tm, an active command may be registered at tm+2, even if (tm+2 - tm) is 2 x tck (avg) + terr(2per),min. 35. input clock jitter spec parameter. these parameters and the ones in the table below are referred to as 'input clock jitter spec parameters' and these para meters apply to ddr2-667 and ddr2-800 only. the jitter specified is a random jitter meeting a gaussian distribution. parameter symbol ddr2-667 ddr2-800 units notes min max min max clock period jitter tjit (per) -125 125 -100 100 ps 35 clock period jitter during dll locking period tjit (per, lck) -100 100 -80 80 ps 35 cycle to cycle clock period jitter tjit (cc) -250 250 -200 200 ps 35 cycle to cycle clock period jitter during dll locking period tjit (cc, lck) -200 200 -160 160 ps 35 cumulative error across 2 cycles terr(2per) -175 175 -150 150 ps 35 cumulative error across 3 cycles terr(3per) -225 225 -175 175 ps 35 cumulative error across 4 cycles terr(4per) -250 250 -200 200 ps 35 cumulative error across 5 cycles terr(5per) -250 250 -200 200 ps 35 cumulative error across n cycles, n=6...10, inclusive terr(6~10per) -350 350 -300 300 ps 35 cumulative error across n cycles, n=11...50, inclusive terr(11~50per) -450 450 -450 450 ps 35 duty cycle jitter tjit (duty) -125 125 -100 100 ps 35 b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 40 release h5ps1g83efr series 36. these parameters are specified per their average values, however it is understood that the following relationship between the average timing and the absolute instantaneous timing hold s at all times. (min and max of spec values are to be used for calculations in the table below.) example: for ddr2-667, tch (abs), min = (0.48 x 3000 ps) - 125 ps = 1315 ps 37. thp is the minimum of the absolute half period of the actual input clock. thp is an input parameter but not an input specification parameter. it is used in co njunction with tqhs to deri ve the dram output timing tqh. the value to be used for tqh calculation is determined by the following equation; thp = min (tch (abs), tcl (abs)), where, tch (abs) is the minimum of the actual instantaneous clock high time; tcl (abs) is the minimum of the actual instantaneous clock low time; 38. tqhs accounts for: 1) the pulse duration distortion of on-chip clock circ uits, which represents how well the actual thp at the input is transferred to the output; and 2) the worst case push-out of dqs on one transition followed by the worst case pull-in of dq on the next transition, both of which are independent of each othe r, due to data pin skew, output pattern effects, and p-channel to n-channel variation of the output drivers 39. tqh = thp ? tqhs, where: thp is the minimum of the absolute half period of the actual input clock; and tqhs is the specification value under the max column. {the less half-pulse width distortion present, the larg er the tqh value is; and the larger the valid data eye will be.} examples: 1) if the system provides thp of 1315 ps into a ddr2-667 sdram, the dram provides tqh of 975 ps min - imum. 2) if the system provides thp of 1420 ps into a ddr2-667 sdram, the dram provides tqh of 1080 ps minimum. 40. when the device is operated with input clock jitter, this parameter needs to be derated by the actual terr(6-10per) of the input clock. (output dera tings are relative to the sdram input clock.) for example, if the measured jitter into a ddr 2-667 sdram has terr(6-10per),min = - 272 ps and terr(6-10per), max = + 293 ps, then tdqsck, min (derated) = tdqsck, min - terr(6-10per),max = - 400 ps - 293 ps = - 693 ps and tdqsck, max (derated ) = tdqsck, max - terr(6-10per),min = 400 ps + parameter symbol min max units absolute clock period tck (abs) tck (avg), min + tjit (per), min tck (avg), max + tjit (per), max ps absolute clock high pulse width tch (abs) tch (avg), min * tck (avg), min + tjit (per), min tch (avg), max * tck (avg), max + tjit (per), max ps absolute clock low pulse width tcl (abs) tcl (avg), min * tck (avg), min + tjit (per), min tcl (avg), max * tck (avg), max + tjit (per), max ps b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 41 release h5ps1g83efr series 272 ps = + 672 ps. similarly, tlz (dq) for ddr2-667 derates to tlz (dq), min (derated) = - 900 ps - 293 ps = - 1193 ps and tlz (dq), max (derated) = 450 ps + 272 ps = + 722 ps. (caution on the min/max usage!) 41. when the device is operated with input clock jitter, this parameter needs to be derated by the actual tjit (per) of the input clock. (output derati ngs are relative to the sdram input clock.) for example, if the measured jitter into a ddr2-667 sd ram has tjit (per), min = - 72 ps and tjit (per), max = + 93 ps, then trpre, min (derated) = trpre, min + tjit (per), min = 0.9 x tck (avg) - 72 ps = + 2178 ps and trpre, max (derated) = trpre, max + tj it (per), max = 1.1 x tck (avg) + 93 ps = + 2843 ps. (caution on the min/max usage!) 42. when the device is operated with input clock jitter, this parameter needs to be derated by the actual tjit (duty) of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2-667 sdram has tjit (duty), min = - 72 ps and tjit (duty), max = + 93 ps, then trpst, min (derated) = trpst, min + tjit (duty), min = 0.4 x tck (avg) - 72 ps = + 928 ps and trpst, max (derated) = trpst, max + tjit (duty), max = 0.6 x tck (avg) + 93 ps = + 1592 ps. (caution on the min/max usage!) 43. when the device is operated with input clock jitter, this parameter needs to be derated by {- tjit (duty), max - terr(6-10per),max} and {- tjit (d uty), min - terr(6-10per),min} of the actual input clock.(output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2- 667 sdram has terr(6-10per),min = - 272 ps, terr(6- 10per), max = + 293 ps, tjit (duty), min = - 106 ps and tjit (duty), max = + 94 ps, then taof, min (der - ated) = taof, min + {- tjit (duty), max - terr(6-10p er),max} = - 450 ps + {- 94 ps - 293 ps} = - 837 ps and taof, max (derated) = taof, max + {- tjit (duty), min - terr(6-10per),min} = 1050 ps + {106 ps + 272 ps} = + 1428 ps. (caution on the min/max usage!) 44. for taofd of ddr2-400/533, the 1/2 clock of tck in the 2.5 x tck assumes a tch, input clock high pulse width of 0.5 relative to tck. taof, min and ta of, max should each be de rated by the same amount as the actual amount of tch offset present at the dram input with respect to 0.5. for example, if an input clock has a worst case tch of 0.45, the taof, min sh ould be derated by subtracting 0.05 x tck from it, whereas if an input clock has a worst case tch of 0.55, the taof, max should be derated by adding 0.05 x tck to it. therefore, we have; taof, min (derated) = tac, min - [0.5 - min(0.5, tch, min)] x tck taof, max (derated) = tac, max + 0.6 + [max(0.5, tch, max) - 0.5] x tck or taof, min (derated) = min (tac, min, tac, min - [0.5 - tch, min] x tck) taof, max (derated) = 0.6 + max (tac, max, tac, max + [tch, max - 0.5] x tck) where tch, min and tch, max are the minimum and maximum of tch actually measured at the dram input balls. 45. for taofd of ddr2-667/800, the 1/2 clock of nck in the 2.5 x nck assumes a tch (avg), average input clock high pulse width of 0.5 relative to tck (avg). taof, min and taof, max should each be derated by the same amount as the actual amount of tch (avg) offset present at the dram input with respect to 0.5. for example, if an input clock has a worst case tch (avg) of 0.48, the taof, min should be derated by sub - b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 42 release h5ps1g83efr series tracting 0.02 x tck (avg) from it, whereas if an input clock has a worst case tch (avg) of 0.52, the taof, max should be derated by adding 0.02 x tck (avg) to it. therefore, we have; taof, min (derated) = tac, min - [0.5 - min(0.5, tch (avg), min)] x tck (avg) taof, max (derated) = tac, max + 0.6 + [max(0.5, tch (avg), max) - 0.5] x tck (avg) or taof, min (derated) = min (tac, min, tac, min - [0.5 - tch (avg), min] x tck (avg)) taof, max (derated) = 0.6 + max (tac, max, tac, max + [tch (avg), max - 0.5] x tck (avg)) where tch (avg), min and tch (avg), max are the mi nimum and maximum of tch (avg) actually measured at the dram input balls. note that these deratings are in addition to the taof derating per input clock jitter, i.e. tjit (duty) and terr(6-10per). however tac values used in the eq uations shown above are from the timing parameter table and are not derated. thus the final derated values for taof are; taof, min (derated _ final) = taof, min (derat ed) + {- tjit (duty), max - terr(6-10per),max} taof, max (derated _ final) = taof, max (derated) + {- tjit (duty), min - terr(6-10per),min} b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 this document is a general product description and is subject to change without notice. hynix semiconductor does not assume any responsibility for use of circuits descr ibed. no patent licenses are implied. rev. 1.1 / oct. 2010 43 h5ps1g83efr series 1gb ddr2 sdram ddr2-1066 b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 44 release h5ps1g83efr series for purposes of idd testing, the follo wing parameters are to be utilized detailed idd7 the detailed timings are shown below for idd7. changes will be required if timi ng parameter changes are made to the specification. legend: a = active; ra = read with autoprecharge; d = deselect idd7: operating current: all bank interleave read operation all banks are being interleaved at minimum t rc(idd) without violating t rrd(idd) using a burst length of 4. control and address bus inputs are stable during deselects. iout = 0ma timing patterns for 8 bank devices x8 (1kb page size) -ddr2-1066 all bins: a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d a4 ra4 d d a5 ra5 d d a6 ra6 d d a7 ra7 d d d d d speed bin (cl-trcd-trp) ddr2-1066 units 7-7-7 cl(idd) 7 tck t rcd(idd) 13.125 ns t rc(idd) 58.125 ns t rrd(idd)-x8 7.5 ns t faw-x8 35 ns t ck(idd) 1.875 ns t rasmin(idd) 45 ns t rasmax(idd) 70000 ns t rp(idd) 13.125 ns t rfc(idd)-256mb 75 ns t rfc(idd)-512mb 105 ns t rfc(idd)-1gb 127.5 ns b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 45 release h5ps1g83efr series 3.5. input/output capacitance 4. electrical characteristics & ac timing specification ( 0 t case 95; v ddq = 1.8 v +/- 0.1v; v dd = 1.8v +/- 0.1v) refresh parameters by device density ddr2 sdram speed bins and trcd, trp and trc for corresponding bin parameter symbol ddr2- 1066 units min max input capacitance, ck and ck cck 1.0 2.0 pf input capacitance delta, ck and ck cdck x 0.25 pf input capacitance, all other input-only pins ci 1.0 1.75 pf input capacitance delta, all other input-only pins cdi x 0.25 pf input/output capacitance, dq, dm, dqs, dqs cio 2.5 3.5 pf input/output capacitance delta, dq, dm, dqs, dqs cdio x 0.5 pf parameter symbol 256mb 512mb 1gb 2gb 4gb units refresh to active ? /refresh command time trfc 75 105 127.5 195 327.5 ns average periodic refresh interval trefi 0 t case 8 5 7.8 7.8 7.8 7.8 7.8 us 85 < t case 95 3.9 3.9 3.9 3.9 3.9 us speed ddr2-1066 units bin(cl-trcd-trp) 7-7-7 parameter min cas latency 7tck trcd : act to rd(a) or wt(a) delay 13.125 ns trp : pre to act delay 13.125 ns tras : act to pre delay 45 min / 70000 max ns trc : act to act delay 58.125 ns tck(avg) @ cl=7 1.875 min / 7.5 max ns b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 46 release h5ps1g83efr series timing parameters by speed grade (refer to notes for information related to this table at the following pages of this table) parameter symbol ddr2-1066 unit note min max dq output access time from ck/ck tac -350 +350 ps 35 dqs output access time from ck/ck tdqsck -325 +325 ps 35 ck high-level width tch 0.48 0.52 tck 30, 31 ck low-level width tcl 0.48 0.52 tck 30, 31 ck half period thp min (tcl,tch) - ps 32 clock cycle time, cl=x tck 1875 7500 ps 30, 31 dq and dm input setup time ? (differential strobe) tds ? (base) 0 - ps 6,7,8, 17, 23, 26 dq and dm input hold time ? (differential strobe) tdh ? (base) 75 - ps 6,7,8, 16, 23, 26 control & address input pulse width for each input tipw 0.6 - tck(avg) dq and dm input pulse width for each input tdipw 0.35 - tck(avg) data-out high-impedance time from ck/ck thz - tac max ps 15, 35 dqs low-impedance time from ck/ck tlz(dqs) tac min tac max ps 15, 35 dq low-impedance time from ck/ck tlz(dq) 2*tac min tac max ps 15, 35 dqs-dq skew for dqs and associated dq signals tdqsq - 175 ps 11 dq hold skew factor tqhs - 250 ps 33 dq/dqs output hold time from dqs tqh thp - tqhs - ps 34 first dqs latching transition to associated clock edge tdqss -0.25 + 0.25 tck(avg) 25 dqs input high pulse width tdqsh 0.35 - tck(avg) dqs input low pulse width tdqsl 0.35 - tck(avg) dqs falling edge to ck setup time tdss 0.2 - tck(avg) 25 dqs falling edge hold time from ck tdsh 0.2 - tck(avg) 25 mode register set command cycle time tmrd 2 - tck write postamble twpst 0.4 0.6 tck(avg) 10 write preamble twpre 0.35 - tck(avg) address and control input setup time tis(base) 125 - ps 5,7,9, 19, 24 address and control input hold time tih(base) 200 - ps 5,7,9, 20, 24 b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 47 release h5ps1g83efr series -continue- (refer to notes for information related to this table at the following pages of this table) parameter symbol ddr2-1066 unit note min max read preamble trpre 0.9 1.1 tck(avg) 16, 36 read postamble trpst 0.4 0.6 tck(avg) 16, 37 active to active command period for 2kb page size products trrd 7.5 - ns 4, 27 four active window for 2kb page size products tfaw 35 - ns 27 cas to cas command delay tccd 2 tck write recovery time twr 15 - ns 27 auto precharge write recovery + precharge time tdal wr+trp - tck 28 internal write to read command delay twtr 7.5 - ns 21, 27 internal read to precharge command delay trtp 7.5 ns 3, 27 exit self refresh to a non-read command txsnr trfc + 10 ns 27 exit self refresh to a read command txsrd 200 - tck exit precharge power down to any non-read command txp 3 - tck exit active power down to read command txard 3 tck 1 exit active power down to read command (slow exit, lower power) txards 10 - al tck 1, 2 cke minimum pulse width (high and low pulse width) t cke 3 tck 22 odt turn-on delay t aond 22tck13 odt turn-on t aon tac(min) tac(max) +2.575 ns 6, 13, 35 odt turn-on(power-down mode) t aonpd tac(min)+2 3tck+ tac(max)+1 ns odt turn-off delay t aofd 2.5 2.5 tck 14, 39 odt turn-off t aof tac(min) tac(max)+ 0.6 ns 14, 38, 39 odt turn-off (power-down mode) t aofpd tac(min)+2 2.5tck avg+ tac(max)+1 ns odt to power down en try latency tanpd 4 tck odt power down exit latency taxpd 11 tck ocd drive mode output delay toit 0 12 ns 27 minimum time clocks remains on after cke asynchronously drops low tdelay tis+tck(avg) +tih ns 12 b48614/178.104.2.80/2010-10-01 14:50
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 48 release h5ps1g83efr series general notes, which may apply for all ac parameters 1. slew rate measurement levels a. output slew rate for falling and rising edges is meas ured between vtt - 250 mv and vtt + 250 mv for single ended ? signals. for differential signals (e.g. dqs - dqs ) output slew rate is measured between dqs - dqs = -500 mv and dqs ? - dqs = +500mv. output slew rate is guaranteed by design, but is not necessarily tested on each device. b. input slew rate for single ended signals is measured from dc-level to ac-level: from vil(dc) to vih(ac) for rising edges and from vih(dc) and vil(ac) for falling edges. for differential signals (e.g. ck - ck ) slew rate for rising edges is measured from ck - ck = -250 mv to ck - ck = ? +500 mv(250mv to -500 mv for falling egdes). c. vid is the magnitude of the di fference between the input voltage on ck and the input voltage on ck , or between ? dqs and dqs for differential strobe. 2. ddr2 sdram ac timing reference load the following figure represents the timing reference load used in defining the relevant timing parameters of the part. it is not intended to be either a prec ise representation of the typical system environment nor a depiction of the actual load presented by a production tester. system designers will use ibis or other simulation tools to correlate the timing reference load to a system environment. manufacturers will correlat e to their production test conditions (generally a coaxial transmission line terminated at the tester electronics) . the output timing reference voltage level for single ended si gnals is the crosspoint with vtt. the output timing refer- ence voltage level for differential signals is the crosspoint of the true (e.g. dqs) and the complement (e.g. dqs) ? signal. 3. ddr2 sdram output slew rate test load output slew rate is characterized unde r the test conditions as shown below. 4. differential data strobe ddr2 sdram pin timings are specified for either single ende d mode or differential mode depending on the setting of the emrs ?enable dqs? mode bit; timing advantages of di fferential mode are realized in system design. the method by which the ddr2 sdram pin timings are measured is mode dependent. in single vddq dut dq dqs dqs rdqs rdqs output v tt = v ddq /2 25 ? timing reference point ac timing reference load vddq dut dq dqs, dqs rdqs, rdqs output v tt = v ddq /2 25 ? test point slew rate test load b48614/178.104.2.80/2010-10-01 14:51
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 49 release h5ps1g83efr series vref. in differential mode, these timing relationships are me asured relative to the crosspoint of dqs and its comple- ment, dqs . this distinction in timing methods is guaranteed by design and characterization. note that when differen- tial data strobe mode is disabled vi a the emrs, the complementary pin, dqs , must be tied externally to vss through a 20 ohm to 10 k ohm resistor to insure proper operation. 5. ac timings are for linear signal transitions. see system derating for other signal transitions. 6. all voltages referenced to vss. 7. these parameters guarantee device behavior, but they are not necessarily tested on each device. they may be guaranteed by device design or tester correlation. 8. tests for ac timing, idd, and electrical (ac and dc) characteristics, may be conducted at nominal reference/ supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. t ds t ds t dh t wpre t wpst t dqsh t dqsl dqs dqs d dmin dqs/ dq dm t dh figure -- data input (write) timing dmin dmin dmin d d d dqs v ih (ac) v il (ac) v ih (ac) v il (ac) v ih (dc) v il (dc) v ih (dc) v il (dc) t ch t cl ck ck ck/ck dqs/dqs dq dqs dqs t rpst q t rpre t dqsqmax t qh t qh t dqsqmax figure -- data output (read) timing q qq b48614/178.104.2.80/2010-10-01 14:51
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 50 release h5ps1g83efr series specific notes for de dicated ac parameters 1. user can choose which active power down exit timing to us e via mrs(bit 12). txard is expected to be used for fast active power down exit timing. txards is expected to be used for slow active power down exit timing where a lower power value is defined by each vendor data sheet. 2. al = additive latency 3. this is a minimum requirement. mini mum read to precharge timing is al + bl/2 providing the trtp and tras(min) have been satisfied. 4. a minimum of two clocks (2 * tck) is re quired irrespective of operating frequency 5. timings are guaranteed with command/a ddress input slew rate of 1.0 v/ns. see system derating for other slew rate values. 6. timings are guaranteed with data, mask, and (dqs/rdq s in singled ended mode) input slew rate of 1.0 v/ns. see system derating for other slew rate values. 7. timings are guaranteed with ck/ck differential slew rate of 2.0 v/ns. timings are guaranteed for dqs signals with a differen tial slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1v/ns in single ended mode. see system derating for other slew rate values. 1) for all input signals the total tis(setup time) and ti h(hold) time) required is calculated by adding the datasheet value to the derating value listed in above table. ? ? setup(tis) nominal slew rate for a rising signal is de fined as the slew rate between the last crossing of v ref (dc) and the first crossing of v ih (ac)min. setup(tis) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref (dc) and the first crossing of v il (ac)max. if the actual signal is always earlier than the nominal slew rate for line between shaded ?v ref (dc) to ac region?, use nominal slew rate for derating value(see fig a.) if the actual signal is later than the nominal slew rate line anywhere between shaded ?v ref (dc) to ac region?, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value(see fig b.) hold(tih) nominal slew rate for a rising signal is de fined as the slew rate between the last crossing of vil(dc)max and the first crossing of v ref (dc). hold(tih) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref (dc). if the actual signal is always later than the nominal slew rate line between shaded ?dc to v ref (dc) region?, use nominal slew ra te for derating value(see fig.c) tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh 2.0 100451004510045------------ 1.5 6721672167217933---------- 1.0 00000012122424 -------- 0.9 ---5-14-5-147-219103122------ 0.8 -----13-31-1-1911-72353517---- 0.7 -------10-422-3014-1826-6386-- 0.6 ---------10-592-4714-3526-2338-11 0.5 -----------24-89-12-770-6512-53 0.4 -------------52-140-40-128-28-116 tds, tdh derating values for ddr2-1066(all units in 'ps', note 1 applies to entire table) 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns 4.0 v/ns 3.0 v/ns 0.8 v/ns dq slew rate v/ns dqs, dqs differential slew rate 2.0 v/ns 1.8 v/ns b48614/178.104.2.80/2010-10-01 14:51
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 51 release h5ps1g83efr series if the actual signal is earlier than the nominal slew rate line anywhere between shaded ?dc to v ref (dc) region?, the slew rate of a tangent line to the actual signal from the dc level to v ref (dc) level is used for derating value(see fig d.) ? ? although for slow rates the total setup time might be negative(i.e. a valid input signal will not have reached v ih/il (ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach v ih/il (ac). for slew rates in between the values listed in table, the derating values may obtained by linear interpola- tion. these values are typically not subject to production te st. they are verified by design and characterization. b48614/178.104.2.80/2010-10-01 14:51
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 52 release h5ps1g83efr series fig. a illustration of nomi nal slew rate for tis,tds ck,dqs v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max vss delta tf delta tr v ref to ac region nominal slew rate nominal slew rate t is , t ds v ref (dc)-v il (ac)max setup slew rate falling signal = delta tf v ih (ac)min-v ref (dc) setup slew rate rising signal = delta tr t ih , t dh t is , t ds t ih , t dh ck, dqs b48614/178.104.2.80/2010-10-01 14:51
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 53 release h5ps1g83efr series fig. -b illustration of tangent line for tis,tds ck, dqs v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max vss delta tf delta tr v ref to ac region tangent line tangent line t is , t ds ck, dqs nomial line nominal line delta tr tangent line[v ih (ac)min-v ref (dc)] setup slew rate rising signal = tangent line[v ref (dc)-v il (ac)max] setup slew rate falling signal = delta tf t ih , t dh t is , t ds t ih , t dh b48614/178.104.2.80/2010-10-01 14:51
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 54 release h5ps1g83efr series fig. -c illustration of nominal line for tih, tdh ck, dqs v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max vss delta tr nominal slew rate nominal slew rate t is , t ds v ref (dc)-v il (dc)max hold slew rate rising signal = delta tr v ih (dc)min - v ref (dc) hold slew rate falling signal = delta tf dc to v ref region delta tf ck, dqs t ih , t dh t is , t ds t ih , t dh b48614/178.104.2.80/2010-10-01 14:51
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 55 release h5ps1g83efr series fig. -d illustration of tangent line for tih , tdh ck, dqs v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max vss delta tf tangent line tangent line t is , t ds ck, dqs nominal line dc to v ref region nominal line delta tr tangent line[v ih (ac)min-v ref (dc)] hold slew rate falling signal = delta tf tangent line[v ref (dc)-v il (ac)max] hold slew rate rising signal = delta tr t ih , t dh t is , t ds t ih , t dh b48614/178.104.2.80/2010-10-01 14:51
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 56 release h5ps1g83efr series 10. the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 11. tdqsq: consists of data pin skew an d output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mismatch betw een dqs / dqs and associated dq in any given cycle. 12. the clock frequency is allowed to change during self ?refresh mode or precharge power-down mode. in case of clock frequency change during precharge power-down, a sp ecific procedure is required as described in section input clock frequency change during precharge power down . 13. odt turn on time min is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measured from taond, which is interpreted as 2 clock cycles after the clock edge that registered a firs t odt high counting the actual input clock edges. 14. odt turn off time min is when the device starts to turn off odt resistance. odt turn off time max is when the bus is in high impedance. both are measured from taofd, whic h is interpreted as 0.5 x tck( avg) [ns] after the second trailing clock edge counting from the cloc k edge that registered a first odt low and by counting the actual input clock edges. for ddr2-1066, this is 0.9375 [ns] (= 0.5 x 1.875 [ns]) after the second tr ailing clock edge counting from the clock edge that registered a first odt low an d by counting the actual input clock edges. 15. thz and tlz transitions occur in the same access ti me as valid data transitions. thesed parameters are referenced to a specific voltage level which specifies wh en the device output is no longer driving(thz), or begins driving (tlz). below figure shows a method to calculate the point when device is no longer driving (thz), or begins driving (tlz) by measuring the signal at two different voltages. the actual voltage mea- surement points are not critical as lo ng as the calculat ion is consistenet. 16. trpst end point and trpre begin point are not refere nced to a specific voltage level but specify when the device output is no longer driving (trpst), or be gins driving (trpre). below figure shows a method to calculate these points when the device is no longer driving (trpst), or begins driving (trpre). below fig- ure shows a method to calculate these points when the de vice is no longer driving (trpst), or begins driv- ing (trpre) by measuring the signal at two different voltages. the actu al voltage measurement points are not critical as long as the calculation is consistent. thz , trpst end point = 2*t1-t2 tlz , trpre begin point = 2*t1-t2 voh + xmv voh + 2xmv vol + 1xmv vol + 2xmv thz trpst end point vtt + 2xmv vtt + xmv vtt -xmv vtt - 2xmv tlz trpre begin point t1 t1 t2 t2 b48614/178.104.2.80/2010-10-01 14:51
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 57 release h5ps1g83efr series 1 7. input waveform timing tds with differential data stro be enabled mr[bit10]=0, is referenced from the input signal crossing at the vih(ac) level to the differential data strobe crosspoint for a rising sign al, and from the input signal crossing at the vil(ac) level to the diff erential data strobe crosspoint for a fa lling signal applied to the device under test. dqs, dqs signals must be monoto nic between vil(dc)m ax and vih(dc)min. 18. input waveform timing tdh with differential data strobe enabled mr[bit10]=0, is referenced from the differential data strobe crosspoint to the input signal crossing at the vih(dc) level for a fallin g signal and from the differential data strobe crosspoint to the input signal crossing at the vil(dc ) level for a rising signal applied to the device under test. dqs, dqs signals must be monotonic between vil(dc)max and vih(dc)min. 19. input waveform timing is referenced from the input signal crossing at the vih(ac) level for a rising signal and vil(ac) for a falling signal appl ied to the device under test. 20. input waveform timing is referenced from the input signal crossing at the vil(dc) level for a rising signal and vih(dc) for a falling signal appl ied to the device under test. 21. twtr is at lease two clocks (2 x nck) independent of operation frequency. 22. tckemin of 3 clocks means cke must be registered on three consecutive positive clock edges. cke must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. thus, after any cke transition, cke may not transition from its valid level du ring the time period of tis + 2* tck + tih. 23. if tds or tdh is violated, data corru ption may occur and the data must be re-w ritten with valid data before a valid read can be executed. dqs v ddq v ih(ac) min v ih(dc) min tdh tds dqs v ref (dc) v ss v il(dc) max v il(ac) max tdh tds differential input waveform timing b48614/178.104.2.80/2010-10-01 14:51
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 58 release h5ps1g83efr series 24. these parameters are measured from a command/address signal (cke, cs, ras, cas, we, odt, ba0, a0, a1, etc.) transition edge to its respective clock signal (ck/ck) crossing. the spec values are no t affected by the amount of clock jitter applied (i.e. tjit(per), tjit(c c), etc.), as the setup and hold are rela tive to the clock signal crossing that latches the command/address. that is, these parameters should be met whether clock jitter is present or not. 25. these parameters are measured from a data strobe signal ((l/u/r)dqs/dqs ) crossing to its respective clock signal (ck/ck ) crossing. the spec values are not affected by the amou nt of clock jitter applied (i.e. tjit(per), tjit(cc), etc.), as these are relative to the clock signal crossing. that is, these parameters should be met whether clock jitter is present or not. 26. these parameters are measured from a data signal ((l/u) dm, (l/u) dq0, (l/u) dq1, etc.) transition edge to its respective data strobe signal ((l/u/r)dqs/dqs) crossing. 27. for these parameters, the ddr2 sdram device is characterized and verified to support tnparam = ru{tparam / tck(avg)}, which is in clock cy cles, assuming all input clock jitter specifications are satisfied. for example, the device will support tnrp = ru {trp / tck(avg)}, which is in clock cycles, if all input clock jitterspecifications are met. this means: for ddr2-1066 7-7-7, of which trp = 13.125ns, the device will support tnrp =ru{trp / tck(avg)} = 7, i.e. as long as the input clock jitter specifications are met, pre- charge command at tm and active command at tm+7 is valid even if (tm+7 - tm) is less than 13.127ns due to input clock jitter. 28. specific note 28 tdal ? nck ? = wr ? nck ? + tnrp ? nck ? = wr + ru ?? trp ? ps ? / tck(avg) ? ps ??? , where wr is the value programmed in the mode register set and ru stands for round up. example: for ddr2-1066 7-7-7 at tck(avg) = 1.875 ns with wr programmed to 8 nck, tdal = 8 + ru ?? 13.125 ns / 1.875 ns ? ? nck ? = 8 + 7 ? nck ? = 15 ? nck ? 29.new units, ?tck(avg)? and ?nck?, are introduced in ddr2-1066. unit ?tck(avg)? represents the actual tc k(avg) of the input clock under operation. unit ?nck? represents one clock cycle of the input clock, counting the actual clock edges. ex) txp = 3 [nck] means; if power down exit is registered at tm, an active command may be registered at tm+3, even if (tm+3 - tm) is 3 x tck(avg) + terr(3per),min. 30. input clock jitter spec parameter. these parameters an d the ones in the table below are referred to as 'input clock jitter spec parameters' and these parame ters apply to ddr2-1066. the jitter specified is a ran- dom jitter meeting a gaussian distribution. b48614/178.104.2.80/2010-10-01 14:51
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 59 release h5ps1g83efr series 31. these parameters are specified per their average values, however it is understood that the following relationship between the average timing and the absolute instantaneous timing holds at all times. (min and max of spec values are to be used for calculations in the table below. example: for ddr2-1066, tch(abs),min = ( 0.48 x 1875 ps ) - 75 ps = 825 ps 32. thp is the minimum of the absolute ha lf period of the actual input clock. th p is an input parame ter but not an input specification parameter. it is used in conjunction with tqhs to derive the dram output timing tqh. the value to be used for tqh calculation is determined by the following equation; thp = min ( tch(abs), tcl(abs) ), where, tch(abs) is the minimum of the actual instantaneous clock high time; tcl(abs) is the minimum of the ac tual instantaneous clock low time; parameter symbol ddr2-1066 units notes min max clock period jitter t jit(per) -90 90 ps 30 clock period jitter during dll locking period t jit(per,lck) -80 80 ps 30 cycle to cycle clock period jitter t jit(cc) -180 180 ps 30 cycle to cycle clock period jitter during dll lock- ing period t jit(cc,lck) -160 160 ps 30 cumulative error across 2 cycles t err(2per) -132 132 ps 30 cumulative error across 3 cycles t err(3per) -157 157 ps 30 cumulative error across 4 cycles t err(4per) -175 175 ps 30 cumulative error across 5 cycles t err(5per) -188 188 ps 30 cumulative error across n cycles, n=6...10, inclusive t err(6~10per) -250 250 ps 30 cumulative error across n cycles, n=11...50, inclusive t err(11~50per) -425 425 ps 30 duty cycle jitter t jit(duty) -75 75 ps 30 parameter symbol min max units absolute clock period tck(abs) tck(avg),min+tjit(per),min tck(avg),max+tjit(per),max ps absolute clock high pulse width tch(abs) tch(avg),min x tck(avg),min + tjit(duty),min tch(avg),max x tck(avg),max + tjit(duty),max ps absolute clock low pulse width tcl(abs) tcl(avg),min x tck(avg),min + tjit(duty),min tcl(avg),max x tck(avg),max + tjit(duty),max ps b48614/178.104.2.80/2010-10-01 14:51
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 60 release h5ps1g83efr series 33. tqhs accounts for: 1) the pulse duration distortion of on-chip clock circuits, which represents how well the actual thp at the input is transferred to the output; and 2) the worst case push-out of dqs on one transition followed by the worst case pull-in of dq on the next transition, both of which are independ ent of each other, due to data pin skew, output pattern effects, and p-channel to n-channel variat ion of the output drivers 34. tqh = thp - tqhs, where: thp is the minimum of the absolute half period of the actual input clock; and tqhs is the specification value under the max column. {the less half-pulse width distortion present, the larger the tqh value is; and the larger the valid data eye will be.} examples: 1) if the system provides thp of 1315 ps into a ddr2-1066 sdram, the dram provides tqh of 575 ps minimum. 2) if the system provides thp of 900 ps into a ddr2-1066 sdram, the dram provides tqh of 650 ps min- imum. 35. when the device is operated with input clock jitte r, this parameter needs to be derated by the actual terr(6-10per) of the input cloc k. (output deratings are relative to the sdram input clock.) for example, if the meas ured jitter into a ddr2-1066 sdram ha s terr(6-10per),min = - 202 ps and terr(6- 10per),max = + 223 ps, then tdqsck,min(derated) = tdqsck,min - terr(6-10per),max = - 300 ps - 223 ps = - 523 ps and tdqsck,max(der- ated) = tdqsck,max - terr(6-10per),min = 300 ps + 202 ps = + 502 ps. similarly, tlz(dq) for ddr2-1066 derates to tlz(dq),min(derated) = - 700 ps - 223 ps = - 923 ps and tl z(dq),max(derated) = 350 ps + 202 ps = + 552 ps. (cau- tion on the min/max usage!) 36. when the device is operated with in put clock jitter, this parameter needs to be derated by the actual tjit(per) of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2-1066 sd ram has tjit(per),min = - 72 ps and tjit(per),max = + 63 ps, then trpre,min(derated) = trpre,min + tjit(per ),min = 0.9 x tck(avg) - 72 ps = + 1615.5 ps and trpre,max(derated) = trpre,max + tjit(per),max = 1.1 x tck(avg) + 63 ps = + 2125.5 ps. (caution on the min/max usage!) 37 . when the device is operated with input clock jitter, this parameter needs to be derated by the actual tjit(duty) of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2-1066 sdram has tjit(duty),min = - 72 ps and tjit(duty),max = + 63 ps, then trpst,min(derated) = trpst,min + tjit(duty),min = 0.4 x tck(avg) - 72 ps = + 678 ps and trpst,max(der- ated) = trpst,max + tjit(duty),max = 0.6 x tck(avg) + 63 ps = + 1188 ps. (caution on the min/max usage!) b48614/178.104.2.80/2010-10-01 14:51
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 61 release h5ps1g83efr series 38 when the device is operated with input clock jitter, this parameter needs to be derated by { - tjit(duty),max - terr(6-10per),max } and { - tjit(duty),min - terr(6-10per),min } of the actual input cloc k. (output deratings are rel- ative to the sdram input clock.) for example, if the measured jitter into a ddr2-1066 sdram has terr(6-10per),min = - 202 ps, terr(6-10per),max = + 223 ps, tjit(duty),min = - 66 ps and tjit(duty),max = + 74 ps, then taof,min(derated) = taof,min + { - tjit(duty),max - terr(6-10per),max } = - 350 ps + { - 74 ps - 223 ps} = - 647 ps and taof,max(derated) = taof,max + { - tjit(duty),min - terr(6-10per),min } = 950 ps + { 66 ps + 202 ps } = + 1218 ps. (caution on the min/max usage!) 39. for taofd of ddr2-1066, the 1/2 clock of nck in th e 2.5 x nck assumes a tch(avg), average input clock high pulse width of 0.5 relative to tck(avg). taof,min and taof ,max should each be derated by the same amount as the actual amount of tch(avg) offset presen t at the dram input with respect to 0.5. for example, if an input clock has a worst case tch(avg) of 0.48, the taof,min should be derate d by subtracting 0.02 x tck(avg) from it, whereas if an input clock has a worst case tch(avg) of 0.52, the taof,max should be derated by adding 0.02 x tck(avg) to it. there- fore, we have; taof,min(derated) = tac,min - [0.5 - min(0.5, tch(avg),min)] x tck(avg) taof,max(derated) = tac,max + 0.6 + [max(0.5, tch(avg),max) - 0.5] x tck(avg) or taof,min(derated) = min(tac,min, tac,min - [0.5 - tch( avg),min] x tck(avg)) taof,max(derated) = 0.6 + max(tac, max, tac,max + [tch(avg),max - 0.5] x tck(avg)) where tch(avg),min and tch(avg),max are th e minimum and maximum of tch( avg) actually measured at the dram input balls. note that these deratings are in addition to the taof derati ng per input clock jitter, i.e. tjit(duty) and terr(6-10per). however tac values used in the equations shown above ar e from the timing parameter table and are not derated. thus the final derated values for taof are; taof,min(derated_final) = taof,min(d erated) + { - tjit(duty),max - terr(6-10per),max } taof,max(derated_final) = taof,max(derated) + { - tjit(duty),min - terr(6-10per),min } b48614/178.104.2.80/2010-10-01 14:51
a pcpcwm_4828539:wp_0000005wp_0000005 apcpcwm_4828539:wp_0000005wp_000000 5 rev. 1.1 / oct. 2010 62 release h5ps1g83efr series package dimension(x8) 60ball fine pitch ball grid array outline 5. package dimension note: all dimensions are in millimeters. < top view> 8.00 0.10 11.40 0.10 a1 ball mark 1.10 0.10 0.34 0.05 0.15 0.05 2-r0.13max < side view> 0.80 a1 ball mark 1.60 1.60 60x 0.45 0.05 < bottom view> 9 8 7 321 0.80 x 8 = 6.40 2.10 0.10 0.80 a b c d e f g h j k l b48614/178.104.2.80/2010-10-01 14:51

▲Up To Search▲

Price & Availability of H5PS1G83EFR-E3L

	To Download H5PS1G83EFR-E3L Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .